################################################################################
#
#					CMOS Technology Description File
#			
#						Author:	Dr. Hsue, Hua
#
#						   Jan. 29, 1993
#
################################################################################
#
# The line which starts with '#' is a comment line.
#
# This Technology Description File (TDF) is designed to represent all
# technology-related information used in FABRIC system. The syntax of TDF is
# the computer meta language proposed by Wirth, which consists of two types of
# symbols, i.e. "terminal symbols" and "non-terminal symbols". "terminal
# symbols" must be present literally, which are denoted normally by words
# between double quote marks, or words printed in italic font. "non-terminal
# symbols" are denoted by lower-case words. The following meta characters are
# used as separators of both terminal symbols and non-terminal symbols:
# 
#	assignment '=':		the equal-sign means that the succeed symbols before
#						a period dot appears is assigned to the symbol followed
#						by that	'='.
#	alternatives '|':	the vertical bar between symbols denotes the choice of
#						either one symbol or another symbol.
#	repetition '{''}':	curly brackets denote that the symbols in between may
#						be present null or more times.
#	optionality '['']':	square brackets denote that the symbols in between may
#						present.
#	parenthesis '('')':	parenthesis serve for grouping of symbols in meta 
#						character expressions.
#
# The TDF is divided into several groups. Each group starts with a terminal 
# symbol to indicate the starting of a group as well as the group type. A group
# is constructed by multiple lines of "structure". Since FABRIC is a
# layout-based defect and fault analysis tool, i.e. the layout masks data are
# used as the only inputs and no other auxilary data are needed, layout
# extraction must be done before defect analysis starts. Therefore, the mask 
# definitions and transistor structures as well as interconnection structures
# must be detailed in TDF. As the VLSI technology dramatically advanced, there
# are possibly more transistor structures on the same chip, or even some new
# structures that currently we have not ever know. So it is not wise that let 
# software system has the knowledge of knowing "which structure is a transistor"
# or "which structure is an interconnection", or "the poly over a diffusion
# area should be a gate of a transistor". Here we only define several basic 
# groups to identify a layout. There are four basic groups available at this 
# moment, however they are extendable. They are:
#
#	layers:				mask layers definitions
#	elements:			all possible structures serve for "devices" in circuits.
#	ports:				the input/output structures of elements.
#	interconnection:	the interconnection structures of nets in circuits.
#
# Using this technique, new structures can be described in the group to which
# it belongs. Hence, the FABRIC output all described elements and nodes with
# required input and output structures.
#
# With this file, principally circuit can be extracted from layout. However
# another file is needed for a complete circuit representation, i.e. the file
# of indicating I/O and powers signal names, which is named IO file, 
# see $(SYSTEM)/FABRIC/lib/fabric.io for its syntax and example.
#
# Since FABRIC is a defect and fault analysis system, a defect model file is 
# also necessary for correct running of the system. 
# See $(SYSTEM)/FABRIC/lib/fabric.dft for its syntax and sample.
#
#					SYNTAX OF TECHNOLOGY DESCRIPTION FILE
#
#	Technology = 	layers elements ports interconnections
#
#	layers =		"layers:" layer { layer }
#	layer =			name ":" number";"
#	name =			[A-Za-z0-9]*
#	number =		[0-9]+
#	
#	elements =		"elements:" element { element }
#	element =		name ":" layer_ref { layer_ref }";"
#	name =			[A-Za-z0-9]*
#	layer_ref =		name | "!"name
#
#	ports =			"ports:" port { port }
#	port =			name ":" element_name out_layer { out_layer };
#	name =			[A-Za-z0-9]*
#	out_layer =		layer_ref
#
#	interconnections = "interconnections:" connect { connect }
#	connect =		name ":" connect_layer upper_layer lower_layer;
#	name =			[A-Za-z0-9]*
#	connect_layer = name
#	upper_layer =	name
#	lower_layer =	name
#
